ఇంటర్నేషనల్ జర్నల్ ఆఫ్ అడ్వాన్స్మెంట్స్ ఇన్ టెక్నాలజీ
అందరికి ప్రవేశం

నైరూప్య

Dynamic Power Reduction of Digital Circuits by Clock Gating

Padmini G.Kaushik, Sanjay M.Gulhane,Athar Ravish Khan

Clock gating technology can reduce the consumption of clock signals’ switching power of flip-flops. The clock gate enable functions can be identified by Boolean analysis of the logic inputs for all adders. However, the enable functions of clock gate can be further simplified, and the average number of adders driven by enable functions can be improved. In this way, the circuit area can be reduced; therefore, the clock gating can be improved and power saving can be achieved.